| Model: | PE2G4BPFI35 |
|---|---|
| Brand: | silicom |
| Origin: | Made In Israel |
| Category: | Electronics & Electricity / Electronics Stocks |
| Label: | bypass , silicom , PEG4BPFI6 |
| Price: |
¥18000
/ pc
|
| Min. Order: | 1 pc |
| Last Online:02 Jun, 2020 |
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Bypass / Disconnect: |
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Bypass / Disconnect Ethernet ports on Power Fail, System Hangs or Software Application Hangs |
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Software programmable Bypass, Disconnect or Normal Mode |
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On Board Watch Dog Timer (WDT) Controller |
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Software programmable time out interval |
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Software Programmable WDT Enable / Disable counter |
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Software programmable Bypass Capability Enable / Disable |
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Software Programmable Disconnect Capability Enable / Disable |
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Software Programmable mode (Bypass, Normal or Disconnect mode) at Power up |
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Software Programmable mode (Bypass, Normal mode) at Power off |
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Independent Bypass operation in every two ports |
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Emulates standard NIC |
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Performance Features: |
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16 Transmit and Receive queues per port |
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Up to 16 queues of Receive Side Scaling (RSS) minimize CPU utilization across multiple processor systems |
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Support for 8 pools of virtual machine Device Queues ( VMDq) per port |
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Support Direct Cache Access ( DCA) |
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Support Intel I/O AT 2.0 |
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TSO interleaving for reduced latency |
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UDP TSO |
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• Minimized device I/O interrupts using MSI and MSI-X |
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• Offload of TCP / IP / UDP checksum calculation and TCP segmentation |
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• SCTP receive and transmit checksum offload |
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• Packet interrupt coalescing timers (packet timers) and absolute- delay interrupt timers for both transmit and receive operation |
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Fiber Gigabit Ethernet 1000Base-SX: |
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Independently Fiber Gigabit Ethernet channel/s support Gigabit Ethernet 1000Base-SX |
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Small Form Factor (SFF) LC Connectors |
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Fiber Gigabit Ethernet 1000Base-LX: |
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Independently Fiber Gigabit Ethernet channel/s support Gigabit Ethernet 1000Base-LX |
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Small Form Factor (SFF) LC Connectors |
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Common Key features: |
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Host Interface standard support PCI Express 1.1 |
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High performance, reliability, and low power use in Intel 82576 dual integrated MAC + PHY and SERDES chip controller |
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Ultra deep packet buffer per channel lowers CPU utilization |
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Hardware acceleration that can offload tasks from the host processor. The controllers can offload TCP/UDP/IP checksum calculations and TCP segmentation |
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Priority queuing – 802.1p layer 2 priority encoding |
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Virtual LANs –802.1q VLAN tagging |
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Jumbo Frame (9.5KB) |
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802.x flow control |
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PCI-SIG SR IOV (8 VF) |
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Multicast/ broadcast Packet replication |
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Statistics for SNMP |
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Supports Vital Product Data (VPD) |
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Integrated LinkSec security engines |
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Supports IEEE 1588 |
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LEDs indicators for link/Activity/Bypass/ Disconnect Mode status |
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