jlink v8 (中国广东省生产商) - 电子产品存货 - 电子、电力产品「自助贸易」

Revision	Memory download via DCC	ARM7 Memory download	ARM9 Memory download
J-Link Rev. 1-4	185.0 kB/s (4MHz JTAG)	150.0 kB/s (4MHz JTAG)	75.0 kB/s (4MHz JTAG)
J-Link Rev. 5	800.0 kB/s (12MHz JTAG)	720.0 kB/s (12MHz JTAG)	550.0 kB/s (12MHz JTAG)
J-Trace Rev. 1	600.0 kB/s (12MHz JTAG)	420.0 kB/s (12MHz JTAG)	280.0 kB/s (12MHz JTAG)

Please note that the actual speed depends on various factors, such as JTAG, clock speed, host CPU core etc.

JTAG Speed

There are basically three types of speed settings:

Fixed JTAG speed

Automatic JTAG speed

Adaptive clocking

Fixed JTAG speed

The target is clocked at a fixed clock speed. The maximum JTAG speed the target can handle depends on the target itself. In general ARM cores without JTAG synchronization logic (such as ARM7-TDMI) can handle JTAG speeds up to the CPU speed, ARM cores with JTAG synchronization logic (such as ARM7-TDMI-S, ARM946E-S, ARM966EJ-S) can handle JTAG speeds up to 1/6 of the CPU speed. JTAG speeds of more than 10 MHz are not recommended.

Automatic JTAG speed

Selects the maximum JTAG speed handled by the TAP controller.

NOTE:
On ARM cores without synchronization logic, this may not work reliably, since the CPU core may be clocked slower than the maximum JTAG speed.

Adaptive clocking

If the target provides the RTCK signal, select the adaptive clocking function to syn- chronize the clock to the processor clock outside the core. This ensures there are no synchronization problems over the JTAG interface.

NOTE:
If you use the adaptive clocking feature, transmission delays, gate delays, and synchronization requirements result in a lower maximum clock frequency than with non-adaptive clocking. Do not use adaptive clocking unless it is required by the hardware design.

Using J-Link

Installing the kernel mode driver
In order to use J-Link, a the kernel mode USB driver jlink.sys needs to be installed. This is done by right clicking on the jlink.inf file and selecting "Install" from the context menu, or by connecting J-Link to a USB port of the Host PC and then referring to the inf file. An installation utility is to come up soon.

Checking functionality

The Jlink.exe file can be used to connect to the ARM chip. It currently permits only simple commands, such as memory dump, halt, step, go, Id-check. This can be used to verify proper installation of the USB driver and to verify the connection to the ARM chip, as well as for simple analysis of the target system.

JTAG interface connection (20 pin)

There is a standard 20 pin connector defined by ARM. J-Link ARM has a built-in 20-pin JTAG connector, which is compatible with this standard.

JTAG interface connector signals :

Pin	Signal	Type	Description
1	VTref	Input	This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.
2	Vsupply	NC	This pin is not connected in J-Link. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.
3	nTRST	Output	JTAG Reset. Output from J-Link to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.
5	TDI	Output	JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU.
7	TMS	Output	JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU.
9	TCK	Output	JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU.
11	RTCK	Input	Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.
13	TDO	Input	JTAG data output from target CPU. Typically connected to TDO on target CPU.
15	RESET	I/O	Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".
17	DBGRQ	NC	This pin is not connected in J-Link. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.
19	5V-Supply	Output	This pin is used to supply power to some eval boards. Not all J-Links supply power on this pin, only the KS (Kickstart) versions. Typically left open on target hardware.

Notes

All pins marked NC are not connected inside J-Link. Any signal can be applied here; J-Link will simply ignore such a signal.

All GND pins must be connected to 0V on the target board.

Pin 19 (VCCS) is used to supply J-Link's target interface. J-Link itself is USB powered, only the target interface is powered thru this pin. Should be connected to target CPUs supply voltage (VCC) and should be between 1.8 and 3.3 V.

Pin 2 is not connected inside J-Link. A lot of targets have pin 1 and pin 2 connected. Some targets use pin 2 instead of pin 1 to supply VCC. These targets will not work with J-Link, unless Pin 1 and Pin 2 are connected on the target's JTAG connector.

Pin 3 (TRST) should be connected to target CPUs TRST pin (sometimes called NTRST). J-Link will also work if this pin is not connected, but you may experience some limitations when deb ing. TRST should be separate from the CPU Reset (pin 15)

Pin 11 (RTCK) should be connected to RTCK if available, otherwise to GND.

Multiple devices in the scan chain

J-Link ARM can handle multiple devices in the scan chain. This applies to hardware where multiple chips are connected to the same JTAG connector. As can be seen in the drawing below, the TCK and TMS lines of all JTAG device are connected, while the TDI and TDO lines form a bus.

Currently, up to 8 devices in the scan chain are supported. One or more of these devices can be ARM cores; the other devices can be of any other type but need to comply with the JTAG standard.

Multi core deb ing

J-Link is able to debug multiple cores on one target system connected to the same scan chain.

How multi-core deb ing works

Multi-core deb ing requires multiple deb ers or multiple instances of the same deb er. Two or more deb ers can use the same J-Link / J-Trace simultaneously. Configuring a deb er to work with a core in a multi-core environment does not require special settings. All that is required is proper setup of the scan chain for each deb er. This enables J-Link / J-Trace to debug more than one core on a target at the same time.
Both deb ers share the same physical connection.

J-Link Server

It allows using the J-Link via TCP/IP, which allows connecting to and fully using a J-Link connected to the USB port of an other computer. Performance is just slightly (about 10%) lower than with direct USB connection. The J-Link server is free and included in the software package available for download.

Specifications

Power Supply	USB powered <50mA
USB Interface	USB 2.0, full speed
Target Interface	JTAG 20-pin (14-pin adapter available)
Serial Transfer Rate between J-Link and Target	up to 12MHz
Supported Target Voltage	1.2 - 3.3 V (5V adapter available)
Operating Temperature	+ 5 °C ... + 60 °C
Storage Temperature	- 20 °C ... + 65 °C
Relative Humidity (non-condensing)	< 90% rH
Size (without cables)	100 x 53x 27mm
Weight (without cables)	70g
Electromagnetic Compatibility (EMC)	EN 55022, EN 55024
Supported OS	Microsoft Windows 2000 Microsoft Windows XP Microsoft Windows XP x64 Microsoft Windows 2003 Microsoft Windows 2003 x64 Microsoft Windows Vista Microsoft Windows Vista x64