深圳市立維創展獨家代理MD657B  12位高速DAC 芯片 

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md657b是高速的12位數字到模擬轉換器（DAC）集成了 

 48:12（4:1 12通道）輸入多路復用器

High-Speed 5.5 GHz Ultra-Broadband MUXDAC

with Analog Output Mode Selections

高速5.5 GHz的超寬帶muxdac

模擬輸出模式選擇

48:12 Input Multiplexer

12-bit 5.5-Gsps DAC with Analog Output format selectable

between Normal-Hold mode or Return-to-Zero mode

Up to 3 rd Nyquist Band Usable Analog Outputs

48:12輸入多路復用器

12位DAC模擬輸出格式可選5.5-gsps

在正常保持模式或返回到零模式

多達3路奈奎斯特頻段可用模擬輸出

 

MD657B 的 PRODUCT  D ESCRIPTION

The  MD657B is a high-speed 12-bit Digital to Analog Converter (DAC) integrated with a

48:12 (12 channels of 4:1) input multiplexer.  The on-chip DAC  can be operated at a

sampling rate up to at least 5.5 Gsps. The analog outputs of DAC can be selected between

Normal-Hold mode (for the 1 st Nyquist band) or Return-to-Zero mode (for the 1 st , 2 nd and

3 rd Nyquist band) operation. Combining with selectable filters,  effectively ultra-broadband

signals from DC to the 3 rd Nyquist band can be generated.  The differential digital data input

interfaces are LVDS, LVPECL and CML compatible. After the 48 pairs of differential

data inputs are multiplexed up to 4 times of speed, the 12 high speed data bits are latched

and encoded to drive the DAC output stage. To minimize the glitch energy and to achieve

high linearity, the DAC is based on a 4-bit segmented and 8-bit R-2R architecture.

Complementary outputs are available with 50-Ω output back terminations. Divide-by-4

clock LVDS outputs and sampling phase selection ( SEL1 and  SEL2 ) are provided to ease

the alignment of sampling phase relative to the input data. Divide-by-8 clock LVDS

outputs are also provided. For system applications which need multiple synchronized

MD657B ‘s, a  RESET function is provided to start all  MD657B ‘s at the same sampling

phase assuming all chips use the same  SEL1 &  SEL2 settings.  DCTL pin can be used to

fine tune the delay between multiple chips within 90 ps range.

MD657B 的產品描述 

md657b是高速的12位數字到模擬轉換器（DAC）集成了 

 48:12（4:1 12通道）輸入多路復用器。片上DAC可以運行在一個 

 采樣率高達至少5.5 GSPS。DAC的模擬輸出可以選擇之間 

 正常的保持模式（1 ST奈奎斯特頻段）或歸零方式（為1、2和 

 3路奈奎斯特帶）操作。結合可選的過濾器，有效的超寬帶 

 從直流到3路奈奎斯特頻段信號可以產生。差分數字數據輸入 

 接口LVDS，LVPECL，CML兼容。48雙微分后 

 數據輸入多路復用高達4倍的速度，12個高速數據位被鎖存 

 編碼驅動DAC輸出階段。為了儘量減少故障能實現 

 高線性度，DAC是基於一個4位的分段和8位R-2R架構。 

 互補輸出可與50Ω輸出端子。分頻4 

 時鐘的LVDS輸出和采樣相位選擇（SEL1和SEL2）提供方便 

 與輸入數據相比較的采樣相位的校準。八分頻時鐘的LVDS 

 輸出也提供。對於需要多個同步的系統應用程序 

 md657b的復位功能是提供給所有md657b開始的在相同的采樣 

 相位假設所有的芯片使用相同的SEL1和SEL2設置。電路引腳可用於 

 微調在90個範圍內的多個芯片之間的延遲。

 

MD657B 的 K EY F EATURES

關鍵特性

• 48:12 input multiplexer

•48:12輸入多路復用器

• 12-bit resolution DAC up to 5.5-Gsps rate

•12位分辨率高達5.5-gsps率

• DAC analog output format can be selected between zero-order Normal-Hold (NH)

•DAC模擬輸出格式可以選擇零階保持正常之間（NH）

mode or Return-to-Zero (RZ) mode

模式或歸零（RZ）模式

• Adjustable clock delay

可調時鐘延遲

• Complementary outputs with 50-Ω back terminations

•互補輸出50Ω回到終端

• Both complementary divide-by-4 and divide-by-8 clock outputs are provided for

•互補分頻4和8分頻時鐘輸出提供

data synchronization

數據同步

• 2.25 W total power consumption

·2.25瓦的總功率消耗

• Variable 400~800 mV PP single-ended output swing

變量400，800 MV的單端輸出擺幅

• On-chip 100 ohm termination between each differential input data and RESET pair

在每一個差分輸入數據和復位對之間的100歐姆終止