The 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 4n prefetch architecture, with an interface designed to transfer four data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM consists of a single 4n-bit wide, one clock cycle data transfer at the internal DRAM core and four corresponding n-bit wide, one-half clock cycle data  transfers at the I/O pins Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the bank and row to be accesses (BA0 & BA1 select the banks, A0-A13 select the row for x4 and x8 components, A0-A12 select the row for x16 components). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the Auto-Precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation.
Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for POWER UP and Initialization.