Quad 2-input OR gate 74HC/HCT32
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT32 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT32 provide the 2-input OR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; t
r = t
f = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC
2
× f
i + ∑ (CL × VCC
2
× fo) where:
f
i = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC
2
× fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
tPHL/ tPLH propagation delay nA, nB to nY CL = 15 pF; VCC = 5 V 6 9 ns
CI
input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per gate notes 1 and 2 16 28 p