The CIR-S2DVSG8002G is 256M words X 64 bits, 2 ranks DDRII SDRAM unbuffered module, mounting 16 pieces of 2Gbits DDR2 SDRAM sealed in FBGA (μBGA®) package. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4bits prefetch pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (μBGA) on the module board.

Specifications

• Density：2GB
• Pin Count：240pin
• Type：Unbuffered
• Dimensions：133.35mm x 18.3mm
• ECC：Non-ECC
• Component Config：128M x 8 bit
• Data Rate：800 MHz
• CAS Latency：6
• Voltage：1.8V
• PCB Layers：6
• Operating Temp.(TCASE)：0°C~+85°C
• Module Ranks：Dual Rank