深圳市立维创展独家代理MD657B  12位高速DAC 芯片 

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md657b是高速的12位数字到模拟转换器（DAC）集成了 

 48:12（4:1 12通道）输入多路复用器

High-Speed 5.5 GHz Ultra-Broadband MUXDAC

with Analog Output Mode Selections

高速5.5 GHz的超宽带muxdac

模拟输出模式选择

48:12 Input Multiplexer

12-bit 5.5-Gsps DAC with Analog Output format selectable

between Normal-Hold mode or Return-to-Zero mode

Up to 3 rd Nyquist Band Usable Analog Outputs

48:12输入多路复用器

12位DAC模拟输出格式可选5.5-gsps

在正常保持模式或返回到零模式

多达3路奈奎斯特频段可用模拟输出

 

MD657B 的 PRODUCT  D ESCRIPTION

The  MD657B is a high-speed 12-bit Digital to Analog Converter (DAC) integrated with a

48:12 (12 channels of 4:1) input multiplexer.  The on-chip DAC  can be operated at a

sampling rate up to at least 5.5 Gsps. The analog outputs of DAC can be selected between

Normal-Hold mode (for the 1 st Nyquist band) or Return-to-Zero mode (for the 1 st , 2 nd and

3 rd Nyquist band) operation. Combining with selectable filters,  effectively ultra-broadband

signals from DC to the 3 rd Nyquist band can be generated.  The differential digital data input

interfaces are LVDS, LVPECL and CML compatible. After the 48 pairs of differential

data inputs are multiplexed up to 4 times of speed, the 12 high speed data bits are latched

and encoded to drive the DAC output stage. To minimize the glitch energy and to achieve

high linearity, the DAC is based on a 4-bit segmented and 8-bit R-2R architecture.

Complementary outputs are available with 50-Ω output back terminations. Divide-by-4

clock LVDS outputs and sampling phase selection ( SEL1 and  SEL2 ) are provided to ease

the alignment of sampling phase relative to the input data. Divide-by-8 clock LVDS

outputs are also provided. For system applications which need multiple synchronized

MD657B ‘s, a  RESET function is provided to start all  MD657B ‘s at the same sampling

phase assuming all chips use the same  SEL1 &  SEL2 settings.  DCTL pin can be used to

fine tune the delay between multiple chips within 90 ps range.

MD657B 的产品描述 

md657b是高速的12位数字到模拟转换器（DAC）集成了 

 48:12（4:1 12通道）输入多路复用器。片上DAC可以运行在一个 

 采样率高达至少5.5 GSPS。DAC的模拟输出可以选择之间 

 正常的保持模式（1 ST奈奎斯特频段）或归零方式（为1、2和 

 3路奈奎斯特带）操作。结合可选的过滤器，有效的超宽带 

 从直流到3路奈奎斯特频段信号可以产生。差分数字数据输入 

 接口LVDS，LVPECL，CML兼容。48双微分后 

 数据输入多路复用高达4倍的速度，12个高速数据位被锁存 

 编码驱动DAC输出阶段。为了尽量减少故障能实现 

 高线性度，DAC是基于一个4位的分段和8位R-2R架构。 

 互补输出可与50Ω输出端子。分频4 

 时钟的LVDS输出和采样相位选择（SEL1和SEL2）提供方便 

 与输入数据相比较的采样相位的校准。八分频时钟的LVDS 

 输出也提供。对于需要多个同步的系统应用程序 

 md657b的复位功能是提供给所有md657b开始的在相同的采样 

 相位假设所有的芯片使用相同的SEL1和SEL2设置。电路引脚可用于 

 微调在90个范围内的多个芯片之间的延迟。

 

MD657B 的 K EY F EATURES

关键特性

• 48:12 input multiplexer

•48:12输入多路复用器

• 12-bit resolution DAC up to 5.5-Gsps rate

•12位分辨率高达5.5-gsps率

• DAC analog output format can be selected between zero-order Normal-Hold (NH)

•DAC模拟输出格式可以选择零阶保持正常之间（NH）

mode or Return-to-Zero (RZ) mode

模式或归零（RZ）模式

• Adjustable clock delay

可调时钟延迟

• Complementary outputs with 50-Ω back terminations

•互补输出50Ω回到终端

• Both complementary divide-by-4 and divide-by-8 clock outputs are provided for

•互补分频4和8分频时钟输出提供

data synchronization

数据同步

• 2.25 W total power consumption

·2.25瓦的总功率消耗

• Variable 400~800 mV PP single-ended output swing

变量400，800 MV的单端输出摆幅

• On-chip 100 ohm termination between each differential input data and RESET pair

在每一个差分输入数据和复位对之间的100欧姆终止